1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package.
2. Description of Related Art
An integrated circuit package is typically formed with a single semiconductor chip. To allow increased functionality and density of electronic components from a single integrated circuit package, it is usually desired and a tendency to pack two or more semiconductor chips rather than just one in an integrated circuit package. An integrated circuit package that packs two integrated circuit chips therein is customarily referred to as a dual-chip integrated circuit package.
The U.S. Pat. No. 5,793,108 discloses a dual-chip integrated circuit package. FIG. 8 is a schematic sectional diagram showing the structure of this dual-chip integrated circuit package. As shown, this dual-chip integrated circuit package includes a leadframe 100 having a die pad 101 for mounting a first integrated circuit chip 120 and a second integrated circuit chip 140. The first integrated circuit chip 120 has its front side 121 attached to the die pad 101 by means of an insulative film 110. The bonding pads 123 on the first integrated circuit chip 120 are electrically connected via a plurality of gold wires 150 to the first surface 102a of the leads 102 of the leadframe 100. An insulative adhesive layer 130 is then coated on the back side 122 of the first integrated circuit chip 120 for attaching the first integrated circuit chip 120 to the back side 142 of the second integrated circuit chip 140. The bonding pads 143 on the front side 141 of the second integrated circuit chip 140 are electrically connected via a plurality of gold wires 160 to a second surface 102b of the leads 102. Further, an encapsulant 170 is formed to encapsulate the first integrated circuit chip 120, the second integrated circuit chip 140, and the inner part of the leads 102. Active circuitry is formed on the front side 121 of the first integrated circuit chip 120 and the front side 141 of the second integrated circuit chip 140.
The forgoing dual-chip integrated circuit package, however, has the following drawbacks. First, it requires the bonding pads 123 on the front side 121 of the first integrated circuit chip 120 to be exposed out of the die pad 101 so as to facilitate the connection of the bonding pads 123 with the gold wires 150. This requires the jointed area between the first integrated circuit chip 120 and the die pad 101 to be smaller than the area of the front side 121 of the first integrated circuit chip 120. However, after the second integrated circuit chip 140 has been attached to the first integrated circuit chip 120, the beneath of the bonding pads 143 on the second integrated circuit chip 140 is a void space without support from the die pad 101. As a consequence, as shown in FIG. 9, during the wire bonding process to connect the bonding wires 160, the second integrated circuit chip 140 is only partly supported by the fixture 180 positioned underneath the die pad 101, which would easily cause the areas near the bonding pads 143 on the second integrated circuit chip 140 and the bonding pads 123 on the first integrated circuit chip 120 to be cracked. Second, since the front side 121 of the first integrated circuit chip 120 is attached to the die pad 101 in a direct face-to-face manner, the first integrated circuit chip 120 could easily subjected to delamination during any temperature change in the manufacture process. This is because that the first integrated circuit chip 120 differs in coefficient of thermal expansion from the die pad 101. The direct face-to-face attachment also requires the insulative film 110 to be large enough to cover the whole of the die pad 101. This practice, however, would considerably increase the manufacture cost. Moreover, the insulative film 110 being made large would hamper the drainage of the air between the insulative tape 110 and the die pad 101 and the air between the insulative tape 110 and the first integrated circuit chip 120, which would undesirably cause voids to be formed in these parts. Under a subsequent high-temperature process condition, the existence of such voids would cause a popcorn effect, which could damage the integrated circuit package structure. Still one drawback is that when the foregoing dual-chip integrated circuit package is made into a low profile device, the gap between the bottom side of the die pad 101 and the bottom of a cavity of an encapsulation mold (not shown) would become very small, causing the flow of the melted molding compound to be slowed down, resulting in the undesired forming of voids in the formed encapsulant. The forming of these voids could also lead to the problem of a popcorn effect.
It is therefore an objective of this invention to provide a dual-chip integrated circuit package, which can help prevent the chips from being cracked during the manufacture process.
It is another objective of this invention to provide a dual-chip integrated circuit package, which can help prevent delamination from occurrence during the manufacture process.
It is still another objective of this invention to provide a dual-chip integrated circuit package, which can help prevent the occurrence of voids in the encapsulant.
In accordance with the foregoing and other objectives, the invention proposes a new dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package.
The dual-chip integrated circuit package of the invention includes: (a) a first integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; (b) a second integrated circuit chip having a front side and a back side, with the front side being formed a plurality of bonding pads; the second integrated circuit chip being attached to the first integrated circuit chip in a back-to-back manner; (c) a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads; at least one support member attached to the front side of the first integrated circuit chip being for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located; (d) a plurality of bonding wires for connecting the bonding pads on the first integrated circuit chip to the first leads and the bonding pads on the second integrated circuit chip to the second leads; (e) at least one insulative adhesive for attaching the support member to the front side of the first integrated circuit chip; and (f) an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe.
The method according to the invention for manufacturing the foregoing dual-chip integrated circuit package includes the following steps: (1) preparing a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads; (2) mounting a first integrated circuit chip onto the support members of the leadframe, the first integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; the first integrated circuit chip being mounted onto the support members in such a manner that the front side thereof faces the support members and the bonding pads on the first integrated circuit chip are separated from any of the support members; (3) performing a first wire-bonding process to connect a plurality of bonding wires between the bonding pads on the first integrated circuit chip and the first leads of the leadframe; (4) mounting a second integrated circuit chip in a back-to-back manner to the first integrated circuit chip; the second integrated circuit chip having a front side and a back side, with the front side thereof being formed with a plurality of bonding pads; the second integrated circuit chip being mounted onto the first integrated circuit chip in such a manner that the back side of the second integrated circuit chip is attached to the back side of the first integrated circuit chip and the bonding pads on the second integrated circuit chip are aligned to at least one of the support members; (5) performing a second wire-bonding process to connect a plurality of bonding wires between the bonding pads on the second integrated circuit chip and the second leads of the leadframe; and (6) performing an encapsulation process to form an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe.
By the invention, only a minor portion of the front side of the first integrated circuit chip comes in touch with the support members; and therefore, it can help prevent delamination from occurring between the first integrated circuit chip and the support members. Moreover, since the total area of the support members is far less than the surface area of the first integrated circuit chip, the insulative films can be very small in size, allowing the utilization of the insulative films in the dual-chip integrated circuit package of the invention to be very cost-effective. In addition, the use of the insulative films to attach the first integrated circuit chip to the support members can help prevent the forming of voids between the insulative films and the first integrated circuit chip and also between the insulative films and the support members. The popcorn effect can thus be prevented.
In the case of the two integrated circuit chips being flash memory chips, each chip is formed with only one row of bonding pads. In this case, it only requires the use of one of the support members attached to the first integrated circuit chip to support the single row of bonding pads on the second integrated circuit chip.
In the case of the first integrated circuit chip being a flash memory chip while the second integrated circuit chip being an ASIC chip, the first integrated circuit chip is formed with only one row of bonding pads while the second integrated circuit chip is formed with two rows of bonding pads. In this case, it requires the use of two support members attached to the first integrated circuit chip to respectively support the two rows of bonding pads on the second integrated circuit chip. Moreover, the second integrated circuit chip should be smaller in dimension than the first integrated circuit chip in the direction extending from the first leads to the second leads of the leadframe, so that the support members can be positioned at a distance away from the bonding pads on the first integrated circuit chip.
In the case of the two integrated circuit chips being ASIC chips, each chip is formed with two rows of bonding pads. In this case, it requires the use of two support members attached to the first integrated circuit chip to respectively support the two rows of bonding pads on the second integrated circuit chip. Moreover, the second integrated circuit chip should be smaller in dimension than the first integrated circuit chip in the direction extending from the first leads to the second leads of the leadframe, so that the support members can be positioned at a distance away from the bonding pads on the first integrated circuit chip and, at the same time, the bonding pads on the second integrated circuit chip can be appropriately supported by the support members.